Integrated circuits grow ever more complex. In particular, very large scale integrated ("VLSI") chip designs grow more complicated every day. It is known in the art to use synthesis algorithms to mathematically evaluate electronic circuits with the help of a computer. In their most simple form, synthesis algorithms express a circuit in terms of a logical truth table and then apply heuristics to the truth table to determine if the circuit can be optimized for various different constraints, such as timing, area, power dissipation, or testability. Synthesis algorithms for the evaluation of chip designs thus are becoming more complex. Accordingly, the complexity of the heuristics (meaning, in general, guidelines or assumptions, based on observed generalities that are not necessarily mathematically precise or fully understood in a scientific sense) applied to the problem of optimal chip design today are vastly more complicated than those available in preceding generations of synthesis tools. However, in the real world, we have neither infinite compute power, infinite time, nor reliable computer systems. We must still be able to turn around the synthesis of large chips rapidly to meet demanding product development schedules.
The traditional way of dealing with these problems is through the introduction of hierarchy in the hardware language ("HDL"). If the pieces of the chip designs being synthesized stay roughly the same size, and it is simply the number of pieces that multiplies to increase the chip design size, then multiple parallel synthesis runs can be used to manage the latency problems of synthesizing the system.
Technology independent optimiztion and technology mapping of large complex integrated circuits can be dealt with effectively in a parallel fashion. However, the timing-correction of a large hierarchical chip design is a difficult problem, which does not succumb to a parallel solution as easily. Unless strict latch-bounding constraints are imposed, it is difficult to resolve the results of timing a piece of a hierarchical chip design by itself (in-vitro) with the results of timing that piece in the context of the timing model of the entire design (in-vivo). The traditional solution to this problem, involves the generation of timing constraints files of arbitrary complexity, specifying factors such as primary input arrival times, transition times, and equivalent drive circuits, primary output required arrival times, and loadings. However, there are always places where the in-vitro timing model using these timing constraints files diverge from the in-vivo.
All effective approaches to timing-correcting large hierarchical structures in parallel also must deal with the parallel-timing-correction convergence problem. Consider the following situation: a hierarchical design with two timing correctable entities. A signal emanates from the first design and is sunk by the second. At the beginning of the first timing-correction iteration, the first design drives the signal out with a high-power buffer. The second immediately buffers that signal and drops it to a number of sinks. This signal is also late, such that timing-correction tries to fix it. Timing correction is run on the first and the second designs in parallel. The timing correction job on the first design decides to eliminate the high-power buffer because the signal is loaded lightly by the second design. Simultaneously, the timing correction job on the second design drops the input buffer because the drive strength of the output buffer driving the signal out of the first design is so high. Both jobs measure that the timing characteristics of the signal in question have improved, where in actuality, when the hierarchy is re-assembled, no progress has been made, and indeed the timing may have gotten worse. If timing-correction is attempted in parallel another time, the reverse happens, and both the input and the output are re-buffered, putting the design back in its original state.
Both the divergence between the timing as measured in the in-vivo versus the in-vitro model, and the parallel-timing-correction convergence problem must be managed appropriately in an effective solution to parallel timing correction of large hierarchical structures.